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ICmic
TM
This X24C02 device has been acquired by IC Microsystems Sdn Bhd from Xicor, Inc.
IC MICROSYSTEMS
2K
X24C02
Serial E PROM
2
256 x 8 Bit
FEATURES
DESCRIPTION
The X24C02 is CMOS a 2048 bit serial E PROM, internally organized 256 x 8. The X24C02 features a serial interface and software protocol allowing operation on a simple two wire bus. Three address inputs allow up to eight
2
*2.7V to 5.5V Power Supply *Low Power CMOS
--Active Current Less Than 1 mA --Standby Current Less Than 50 A *Internally Organized 256 x 8
devices to share a common two wire bus.
Xicor E PROMs are designed and tested for applications requiring extended endurance. Inherent data retention is greater than 100 years. Available in DIP, MSOP and SOIC packages.
2
*Self Timed Write Cycle
--Typical Write Cycle Time of 5 ms *2 Wire Serial Interface --Bidirectional Data Transfer Protocol *Four Byte Page Write Operation --Minimizes Total Write Time Per Byte *High Reliability
--Endurance: 100,000 Cycles --Data Retention: 100 Years
*New Hardwire--Write Control Function
FUNCTIONAL DIAGRAM
(8) V CC (4) V SS
(7) WC START CYCLE (5) SDA
START STOP
H.V. GENERATION TIMING
& CONTROL LOGIC
CONTROL LOGIC
SLAVE ADDRESS REGISTER
(6) SCL (3) A2 (2) A1 (1) A0
+COMPARATOR
LOAD
INC
XDEC
E PROM 64 X 32
2
WORD ADDRESS COUNTER
R/W
YDEC 8 CK PIN DATA REGISTER
D OUT
D
OUT ACK
3838 FHD F01
(c) Xicor, 1991 Patents Pending
3838-1.2 7/30/96 T0/C3/D1 SH
1
Characteristics subject to change without notice
X24C02
PIN DESCRIPTIONS
Serial Clock (SCL) The SCL input is used to clock all data into and out of the device. Serial Data (SDA) SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs. An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the Guidelines for Calculating Typical Values of Bus Pull-Up Resistors graph. Address (A0, A1, A2) The address inputs are used to set the least significant three bits of the seven bit slave address. These inputs can be static or actively driven. If used statically they must be tied to VSS or VCC as appropriate. If actively driven, they must be driven to VSS or to VCC. Write Control (WC) The Write Control input controls the ability to write to the device. When WC is LOW (tied to VSS) the X24C02 will be enabled to perform write operations. When WC is HIGH (tied to VCC) the internal high voltage circuitry will be disabled and all writes will be disabled.
A 0 A 1 A 2 V SS
PIN CONFIGURATION
DIP/SOIC/MSOP 1 2 3 4 X24C02 8 7 6 5
V CC WC
SCL SDA
3838 FHD F02
PIN DESCRIPTIONS Symbol A0-A2 SDA SCL WC VSS VCC Description Address Inputs Serial Data Serial Clock Write Control Ground +5V
3838 PGM T01
2
X24C02
DEVICE OPERATION
The X24C02 supports a bidirectional bus oriented protocol The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. Therefore, the X24C02 will be considered a slave in all applications.
Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. Refer to Figures 1 and 2. Start Condition All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The X24C02 continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met.
Figure 1. Data Validity
SCL
SDA DATA STABLE DATA CHANGE
3838 FHD F06
3
X24C02
The X24C02 will respond with an acknowledge after recognition of a start condition and its slave address. If
Stop Condition All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used by the X24C02 to place the device in the standby power mode after a read sequence. A stop condition can only be issued after the transmitting device has released the bus. Acknowledge Acknowledge is a software convention used to indicate successful data transfer. The transmitting device, either
both the device and a write operation have been selected, the X24C02 will respond with an acknowledge
after the receipt of each subsequent eight bit word.
In the read mode the X24C02 will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the X24C02 will continue to transmit data. If an acknowledge is not detected, the X24C02 will terminate further data transmissions. The master must then issue a stop condition to return the X24C02 to the standby power mode and
master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle the receiver will
pull the SDA line LOW to acknowledge that it received the eight bits of data. Refer to Figure 3.
place the device into a known state.
Figure 2. Definition of Start and Stop
SCL
SDA START BIT STOP BIT
3838 FHD F07
Figure 3. Acknowledge Response From Receiver
SCL FROM MASTER
1
8
9
DATA OUTPUT FROM TRANSMITTER
DATA OUTPUT FROM RECEIVER
START
ACKNOWLEDGE
3838 FHD F08
4
X24C02
DEVICE ADDRESSING
Following a start condition the master must output the address of the slave it is accessing. The most significant four bits of the slave are the device type identifier (see Figure 4). For the X24C02 this is fixed as 1010[B]. Following the start condition, the X24C02 monitors the SDA bus comparing the slave address being transmitted with its slave address (device type and state of A0, A1 and A2 inputs). Upon a correct compare the X24C02 outputs an acknowledge on the SDA line. Depending on the state of the R/W bit, the X24C02 will execute a read or write operation.
Figure 4. Slave Address WRITE OPERATIONS
DEVICE TYPE IDENTIFIER
1
0
1
0
A2
A1
A0
R/W
Byte Write For a write operation, the X24C02 requires a second address field. This address field is the word address,
comprised of eight bits, providing access to any one of the 256 words of memory. Upon receipt of the word
DEVICE ADDRESS
3838 FHD F09
address the X24C02 responds with an acknowledge, and awaits the next eight bits of data, again responding with an acknowledge. The master then terminates the transfer by generating a stop condition, at which time the X24C02 begins the internal write cycle to the nonvolatile memory. While the internal write cycle is in progress the X24C02 inputs are disabled, and the device will not respond to any requests from the master. Refer to Figure 5 for the address, acknowledge and data transfer sequence.
The next three significant bits address a particular device. A system could have up to eight X24C02 devices on the bus (see Figure 10). The eight addresses are defined by the state of the A0, A1 and A2 inputs. The last bit of the slave address defines the operation to be performed. When set to one a read operation is selected, when set to zero a write operations is selected.
Figure 5. Byte Write
S T BUS ACTIVITY: MASTER
A R T S
SLAVE ADDRESS
WORD ADDRESS
DATA
S T
O P
SDA LINE
BUS ACTIVITY: X24C02
P A C K A C K A C K
3838 FHD F010
Figure 6. Page Write
S T BUS ACTIVITY: MASTER
A R
SLAVE ADDRESS
WORD ADDRESS (n)
DATA n
DATA n+1
DATA n+3
S T
O P
T S
A C A C A C A C A C
SDA LINE
BUS ACTIVITY: X24C02
P
K
K
K
K
K
NOTE: In this example n = xxxx 000 (B); x = 1 or 0
3838 FHD F011
5
X24C02
Flow 1. ACK Polling Sequence
Page Write The X24C02 is capable of a four byte page write operation. It is initiated in the same manner as the byte write operation, but instead of terminating the write cycle after the first data word is transferred, the master can transmit up to three more words. After the receipt of each word, the X24C02 will respond with an acknowledge. After the receipt of each word, the two low order address bits are internally incremented by one. The high order six bits of the address remain constant. If the master should transmit more than four words prior to generating the stop condition, the address counter will "roll over" and the previously written data will be overwritten. As with the byte write operation, all inputs are disabled until completion of the internal write cycle. Refer to Figure 6 for the address acknowledge and data transfer sequence.
WRITE OPERATION COMPLETED
ENTER ACK POLLING
ISSUE START
ISSUE SLAVE ADDRESS AND R/W = 0
ISSUE STOP
ACK RETURNED?
NO
Acknowledge Polling The disabling of the inputs, during the internal write operation, can be used to take advantage of the typical 5 ms write cycle time. Once the stop condition is issued to indicate the end of the host's write operation the X24C02 initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address for a write operation. If the X24C02 is still busy with the write operation no ACK will be returned. If the X24C02 has completed the write operation an ACK will be returned and the master can then proceed with the next read or write operation.
YES
NEXT OPERATION
NO
A WRITE? YES
ISSUE BYTE ADDRESS
ISSUE STOP
READ OPERATIONS
Read operations are initiated in the same manner as write operations with the exception that the R/W bit of the slave address is set to a one. There are three basic read operations: current address read, random read and
PROCEED
PROCEED
3838 FHD F12
sequential read.
It should be noted that the ninth clock cycle of the read operation is not a "don't care." To terminate a read operation, the master must either issue a stop condition during the ninth cycle or hold SDA HIGH during the ninth
clock cycle and then issue a stop condition.
6
X24C02
Current Address Read Internally the X24C02 contains an address counter that maintains the address of the last word accessed, incremented by one. Therefore, if the last access (either a read or write) was to address n, the next read operation would access data from address n + 1. Upon receipt of the slave address with the R/W bit set to one, the X24C02 issues an acknowledge and transmits the eight bit word during the next eight clock cycles. The master terminates this transmission by issuing a stop condition, omitting the ninth clock cycle acknowledge. Refer to Figure 7 for the sequence of address, acknowledge and data transfer.
Random Read Random read operations allow the master to access any memory location in a random manner. Prior to issuing the slave address with the R/W bit set to one, the master must first perform a "dummy" write operation. The master ter issues the start condition, and the slave address followed by the word address it is to read. After the word address acknowledge, the master immediately reissues the start condition and the slave address with the R/W bit set to one. This will be followed by an acknowledge from the X24C02 and then by the eight bit word. The master terminates this transmission by issuing a stop condition, omitting the ninth clock cycle acknowledge. Refer to Figure 8 for the address, acknowledge and data transfer sequence.
Figure 7. Current Address Read
S T BUS ACTIVITY: MASTER
A R
SLAVE ADDRESS
DATA
S T
O P
T S
A C
SDA LINE
BUS ACTIVITY: X24C02
P
K
3838 FHD F13
Figure 8. Random Read
S T BUS ACTIVITY: MASTER
A R
SLAVE ADDRESS
WORD ADDRESS n
S T
A R
SLAVE ADDRESS
DATA n
S T
O P
T S
A C A C
T S
A C
SDA LINE
BUS ACTIVITY: X24C02
P
K
K
K
3838 FHD F14
7
X24C02
The data output is sequential, with the data from address and followed by the data from n + 1. The address counter for read operations increments all address bits, allowing the entire memory contents to be serially read during one operation. At the end of the address space (address 255), the counter "rolls over" to address 0 and the X24C02 continues to output data for each acknowledge received. Refer to Figure 9 for the address, acknowledge
Sequential Read Sequential Read can be initiated as either a current address read or random access read. The first word is transmitted as with the other modes, however, the master now responds with an acknowledge, indicating it requires additional data. The X24C02 continues to output data for each acknowledge received. The master terminates this transmission by issuing a stop condition, omitting the ninth clock cycle acknowledge.
and data transfer sequence.
Figure 9. Sequential Read
S T
O P
BUS ACTIVITY: MASTER
SLAVE ADDRESS
A C
A C
A C
K
K
K
SDA LINE
BUS ACTIVITY: X24C02
P
A C
K
DATA n
DATA n+1
DATA n+2
DATA n+x
3838 FHD F15
Figure 10. Typical System Configuration
V CC
SDA SCL MASTER TRANSMITTER/ SLAVE RECEIVER SLAVE TRANSMITTER/ MASTER TRANSMITTER MASTER TRANSMITTER/
RECEIVER
RECEIVER
RECEIVER
3838 FHD F16
8
X24C02
ABSOLUTE MAXIMUM RATINGS* Temperature Under Bias .................. -65C to +135C *COMMENT Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions
Storage Temperature ....................... -65C to +150C Voltage on any Pin with Respect to V SS ................................ -1.0V to +7.0V D.C. Output Current ............................................ 5 mA Lead Temperature (Soldering, 10 Seconds) ..... 300C
for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS Temperature Commercial Industrial Military Min. 0C -40C -55C Max. 70C +85C +125C
3838 PGM T09
Supply Voltage X24C02 X24C02-3.5 X24C02-3 X24C02-2.7
Limits 4.5V to 5.5V 3.5V to 5.5V 3V to 5.5V 2.7 to 5.5V
3838 PGM T10
D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified).
Limits Symbol lCC1 lCC2 ISB(1) ISB(2) ILI ILO VlL(2) VIH(2) VOL Parameter Power Supply Current (read) Power Supply Current (write) Standby Current Standby Current Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Min. Max. 1 2 50 30 10 10 VCC x 0.3 -1.0 VCC x 0.7VCC + 0.5 0.4 Units mA Test Conditions
SCL = VCC x 0.1/VCC x 0.9 Levels @ 100 KHz, SDA = Open, All Other
Inputs = GND or VCC - 0.3V A A A A V V V
SCL = SDA = VCC - 0.3V, All other Inputs = GND or VCC, VCC = 5.5V SCL = SDA = VCC - 0.3V, All Other Inputs = GND or VCC = 3.3V + 10%
VIN = GND to VCC VOUT = GND to VCC
IOL = 3 mA
3838 PGM T02
CAPACITANCE TA = 25C, f = 1 MHz, VCC = 5V
Symbol CI/O(3) CIN(3)
Parameter Input/Output Capacitance (SDA) Input Capacitance (A0, A1, A2, SCL, WC)
Max. 8 6
Units pF pF
Test Conditions VI/O = 0V VIN = 0V
3838 PGM T04
Notes:(1)Must perform a stop command prior to measurement. (2)VIL min. and VIH max. are for reference only and are not tested. (3)This parameter is periodically sampled and not 100% tested.
9
X24C02
A.C. CONDITIONS OF TEST Input Pulse Levels
Input Rise and Fall Times Input and Output Timing Levels
EQUIVALENT A.C. LOAD CIRCUIT
5.0V 1533
VCC x 0.1 to VCC x 0.9
10 ns VCC x 0.5
3838 PGM T05
OUTPUT 100pF
3838 FHD F18
A.C. CHARACTERISTICS (Over recommended operating conditions) DATA INPUT TIMING
Symbol fSCL TI tAA tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO tDH Bus Timing
Parameter SCL Clock Frequency Noise Suppression Time Constant at SCL, SDA Inputs SCL Low to SDA Data Out Valid Time the Bus Must Be Free Before a New Transmission Can Start Start Condition Hold Time Clock Low Period Clock High Period Start Condition Setup Time Data In Hold Time Data In Setup Time SDA and SCL Rise Time SDA and SCL Fall Time Stop Condition Setup Time Data Out Hold Time
Min. 0
Max. 100 100 3.5
Units KHz ns s s s s s s s
0.3 4.7 4.0 4.7 4.0 4.7 0 250
1 300 4.7 300
ns s ns s ns
3838 PGM T06
t
F
t
HIGH
t
LOW
t
R
SCL
t SU:STA t HD:STA t HD:DAT t SU:DAT t SU:STO
SDA IN
t AA t DH t BUF
SDA OUT
3838 FHD F04
POWER-UP TIMING Symbol tPUR(4) tPUW(4) Parameter Power-up to Read Operation Power-up to Write Operation Max. 1 5 Units ms ms
3838 PGM T07
Notes:(4) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. These parameters are periodically sampled and not 100% tested.
10
X24C02
WRITE CYCLE LIMITS Symbol t
(6) WR
Parameter Write Cycle Time
Min.
Typ. 5
(5)
Max. 10
Units ms
3838 PGM T08
The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle, the X24C02 bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.
Write Cycle Timing
SCL
SDA
8th BIT WORD n
ACK
t WR
STOP CONDITION
START CONDITION
X24C02 ADDRESS
3838 FHD F05
Notes: (5)Typical values are for TA = 25 C and nominal supply voltage (5V) (6) tWR is the minimum cycle time from the system perspective when polling techniques are not used. It is the maximum time the device requires to perform the internal write operation.
Guidelines for Calculating Typical Values of Bus Pull-Up Resistors
SYMBOL TABLE
WAVEFORM INPUTS Must be steady May change from Low to High May change from High to Low
Don't Care: Changes
OUTPUTS Will be steady Will change from Low to High Will change from High to Low Changing: State Not Known Center Line is High Impedance
120 RESISTANCE (K) 100 80 60 40 20 0 0 20 40
R MIN
V
=
CC MAX I OL MIN t R C BUS
=1.8K
R MAX
=
MAX. RESISTANCE
MIN. RESISTANCE
60
80100120
Allowed N/A
3838 FHD F17
BUS CAPACITANCE (pF)
11
X24C02
PACKAGING INFORMATION
8-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P
0.430 (10.92) 0.360 (9.14)
0.092 (2.34) DIA. NOM.
0.255 (6.47) 0.245 (6.22)
PIN 1 INDEX PIN 1
0.300 (7.62) REF. 0.060 (1.52) 0.020 (0.51)
HALF SHOULDER WIDTH ON ALL END PINS OPTIONAL SEATING PLANE
0.140 (3.56) 0.130 (3.30)
0.150 (3.81) 0.125 (3.18)
0.020 (0.51) 0.015 (0.38) 0.062 (1.57) 0.058 (1.47)
0.110 (2.79) 0.090 (2.29)
0.020 (0.51) 0.016 (0.41)
0.015 (0.38) MAX.
0.325 (8.25) 0.300 (7.62)
TYP. 0.010 (0.25)
0 15
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
12
X24C02
PACKAGING INFORMATION
8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
0.150 (3.80) 0.158 (4.00) PIN 1 INDEX
0.228 (5.80) 0.244 (6.20)
PIN 1
0.014 (0.35) 0.019 (0.49)
0.188 (4.78) 0.197 (5.00)
(4X) 7
0.053 (1.35) 0.069 (1.75)
0.050 (1.27)
0.004 (0.19) 0.010 (0.25)
0.010 (0.25) X 45 0.020 (0.50)
0 - 8
0.0075 (0.19) 0.010 (0.25)
0.027 (0.683) 0.037 (0.937)
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESIS IN MILLIMETERS)
13
X24C02
PACKAGING INFORMATION
8-LEAD MINIATURE SMALL OUTLINE GULL WING PACKAGE TYPE M
0.118 0.002 (3.00 0.05)
0.012 + 0.006 / -0.002 (0.30 + 0.15 / -0.05)
0.0256 (0.65) TYP
R 0.014 (0.36)
0.118 0.002 (3.00 0.05)
0.030 (0.76) 0.0216 (0.55)
0.036 (0.91) 0.032 (0.81)
7 TYP
0.040 0.002 (1.02 0.05)
0.008 (0.20) 0.004 (0.10)
0.007 (0.18) 0.005 (0.13)
0.150 (3.81) REF. 0.193 (4.90) REF.
NOTE: 1. ALL DIMENSIONS IN INCHES AND (MILLIMETERS)
3003 ILL 01
14
X24C02
NOTES
15
X24C02
ORDERING INFORMATION
X24C02 Device P T G -V VCC Limits Blank = 4.5V to 5.5V 3.5 = 3.5V to 5.5V 3 = 3.0V to 5.5V 2.7 = 2.7V to 5.5V G = RoHS Compliant Lead Free packge Blank = Standard package. Non lead free
Temperature Range Blank = Commercial = 0C to +70C I = Industrial = -40C to +85C
M = Military = -55C to +125C
Package P = 8-Lead Plastic DIP S8 = 8-Lead SOIC M = 8-Lead MSOP
Part Mark Convention X24C02 X G
Blank = 8-Lead SOIC P = 8-Lead Plastic DIP S8 = 8-Lead SOIC M = 8-Lead MSOP G= RoHS compliant lead free
Blank = 4.5V to 5.5V, 0C to +70C I = 4.5V to 5.5V, -40C to +85C
X
M = 4.5V to 5.5V, -55C to 125C B = 3.5V to 5.5V, 0C to +70C C = 3.5V to 5.5V, -40C to +85C D = 3.0V to 5.5V, 0C to +70C E = 3.0V to 5.5V, -40C to +85C F = 2.7V to 5.5V, 0C to +70C
G = 2.7V to 5.5V, -40C to +85C
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied.
U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurence. Xicor's products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
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